SEMICON Korea 2009 Call for Papers

SEMICON Korea 2009 Call for Papers

SEMI Technology Symposium (STS) 2009
SEMICON® Korea 2009
January 20- 22, 2009
COEX, Seoul, Korea

Abstract Deadline: August 31, 2008

Semiconductor Equipment and Materials International (SEMI) is soliciting papers from authors around the world for various technical programs held in conjunction with SEMICON® Korea 2009. Individuals are encouraged to submit original papers related to any of the following categories.

Abstract & Biography Deadline: August 31, 2008

Session 1. Advanced Lithography

  • Resist Processes and Materials
  • Photomask Processes and Materials
  • Lithography Simulation (Wafer/Mask Processes) and Imaging Fundamentals
  • Resolution Enhancement Methods
  • OPC and Design for Manufacturing
  • Immersion Lithography (Water, High Refractive Index Fluid)
  • Multiple Exposure and Double Patterning Techniques
  • Advanced Metrology Technology for Wafer and Mask
  • Extreme Ultraviolet Lithography
  • Nano-Imprint Lithography
  • Alternative Lithography (E-beam, Interferometric, X-ray, Ion-beam, Self-assembly, Maskless Lithography)
  • Applicaiton of Lithography to Nanotechnology

Session 2. Dielectrics, Metals, New Materials and their Processes

    • Advanced Gapfill Technology
    • Interconnection (Cu, Al, W Barrier Metal, Gate Electrode, Salicidation, Optical Interconnection)
    • Dielectric (high k, low k, Gate Dielectric, Ferroelectric, Passivation)
    • 3D Integration and Process Technology (Wafer Bonding, Thinning, TSV, etc)
    • Doping & Heat Treatment Process (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, Damage Control)
    • Epitaxial Growth (Blanket, Selective, Device Integration)
    • SOI Materials & Processes (Wafer Manufacturing, Device Manufacturing)
    • Materials and Process for Non Volatile Memory Devices (PCRAM, STT-RAM, ReRAM, PoRAM, etc)
    • Nano Process Technology (Quantum Dot/Nanowire/Layer Formation)
    • Semiconductor Process for Solar Cell Application

Session 3. Device Technology

    • SoC Technology
    • Advanced CMOS Technology
    • Advanced Memory Technology
    • SOI Devices
    • RF Devices
    • Nano-scale Devices
    • Thin Film Devices
    • Interconnection Technology
    • Advanced Junction/Doping Technology
    • Process/Device/Interconnection Modeling
    • Device/Interconnection Reliability
    • Organic Devices (OLED/Organic TFT)
    • MEMS/Sensor/Medical/Display/Power Devices

Session4. Etching Technology

    • Gate Etch: Flash Floating Gate Etch, Recessed Gate Etch, Fin-FET Etch
    • STI Etch: STI Etch, ILD Etch
    • Mask Etch
    • Deep and Small Contact Etch
    • Damage Free low k Etch
    • New Materials and Novel Metal Etch
    • Soft Treatment Etch
    • TSV(Through Silicon Via) Etch for Multiple Chip Package
    • APC/AEC(Advanced Process Control/Advanced Equipment Control) for Plasma Processes
    • Strategy and Development for High throughput and Low Cost Equipment
    • In-situ Chamber Cleaning and Particle Reduction and Control
    • Chamber Monitoring and In-situ Metrology

Session 5. Contamination-free Manufacturing and CMP Technology

    • Advanced Wet/Dry Surface Preparation in FEOL/BEOL
    • Environmentally Benign Manufacturing/PFC Emission Reduction
    • Micro-, Nano-contamination Control
    • Damage/Loss Free Nano Particle Removal
    • Yield Enhancement Technology
    • Advances in CMP, Related Processes and Equipments
    • CMP Consumables and Metrology
    • Scratch Reduction/Mechanism
    • CMP Modeling and Simulation
    • Post CMP Cleaning

Session 6. Electropackage System and Interconnect Product

    • Advanced Packaging : 3D Packaging, Wafer Level Packaging, CSP, BGA, MCM/KGD, COB/COF/COG, MEMS Packaging, Opto Packaging
    • Interconnections : TSV, Flip Chip, Wire bonding, TAB, SMT
    • Design, Modeling & Simulation: Electrical, Thermal & Mechanical Management, Reliability Simulation
    • Material and Interposer : Si Interposer, EMC/Encapsulants, Lead Frames, Polymers, Substrates, Solders, surface finish, Lead-Free Bumping
    • Reliability and Analysis : Package Related Issues
    • Equipment : Manufacturing Equipment Automation, Inspection, Assembly Cost Reduction

Session 7. Metrology & Inspection Technology

    • Inspection for Below 30 nm Devices (Pattern and Non-pattern defects)
    • Inspection of Non-visual Defects
    • Inspection and Metrology for Wafer Edge Yield Improvement
    • Techniques for Contamination Monitoring (Surface, Layer and Interface)
    • Mask Defect Monitoring Techniques
    • In-Die Metrology of Patterns and Ultra-thin Layers
    • 3D Simulation and Modeling of Nanostructures
    • In-line Electrical Characterization Methods
    • Metrology for New Materials
    • Overlay
    • Metrology and Inspection for Future CMOS

Prospective authors are requested to submit an abstract of 200-250 words and a 100 word biography by August 31, 2008 indicating the category for which the paper is being submitted. All abstract must appear on company letter head which should include complete address, telephone, fax numbers and e-mail address.

Presentations are to be non-commercial in that they will focus on the technical merits rather than on individual company’s product benefits. Selected speakers will be notified by October 31, 2008.

A manuscript and presentation file will be required to submit by November 30, 2008. Please submit the cover sheet, abstracts, and biographies to JoAnn Lee at SEMI Korea.

Accepted papers are subject to co-copyright with SEMI, who reserves the right to republish, re-sell and display submitted material in whole or in part.

JoAnn Lee, SEMI Korea
#4005 Trade Tower
159-1, Samsung-dong, Kangnam-gu
Seoul 135-729 Korea
ph: 82.2.531.7806, fax: 82.2.551.3406
E-mail: julee@semi.org