View the TechXPOTs Slides: Learn about Emerging Tech, Device Scaling and TAP
At SEMICON West 2008, three TechXPOTs, or “Shows within a Show,” featured exhibits, products, free live technical presentations, and more. This year the TechXPOTs focused on Emerging Technologies, Device Scaling, and Test, Assembly, and Packaging. Each one delved deep into the issues, resulting in animated discussion and collaboration. See what it was all about by viewing the presentation slides.
Emerging Technologies TechXPOT
What are market leaders saying about key developments in emerging applications for micro manufacturing technology? What opportunities and challenges do these present for semiconductor equipment and materials suppliers? The Emerging Markets TechXPOT highlights the latest in MEMS applications and technology, solid state lighting, printed and flexible electronics, and energy:
- MEMS Markets, Applications, and Developments: This session provides an update on recent developments in the MEMS/MST market, outlining key developing application areas. To view the “MEMS Market” presentation slides, please click here.
- MEMS Manufacturing and Materials Technologies: Key users and suppliers discuss manufacturing technology for MEMS devices, focusing on: critical materials and key metrology, failure analysis and test controls for efficient production, MEMS packaging and MEMS testing. To view these presentation slides, click here.
- Portable Power: Micro/Nano Manufacturing: Micro/nano manufacturing starts to bring thin film batteries, energy harvesting and portable fuel cells to market. Learn from leading suppliers on the key technologies changing the portable power market, and what that means for the supply chain by clicking here.
- Solid State Lighting: Solid state lighting makers report major improvements in brightness and efficiency. Incentives to cut carbon emissions will push the technology into other markets, creating a $1.4 billion opportunity by 2012. Leading suppliers discuss how the semiconductor supply chain can help meet the demands of the energy-efficient lighting market in these presentations (click here).
- Flexible and Printed Electronics: Industry leaders talk about the manufacturing challenges of dealing with substrates that flex, organic materials that degrade in air, and entirely new applications enabled by ultra-low cost processes (such as roll-to-roll printing of electronic circuits). To view these slides, click here.
Challenges in Device Scaling TechXPOT
As microelectronics enter the nanotechnology era and as Moore’s Law is pushed to its limits and beyond, the technologies involved in scaling devices to 32 nanometers and below remain at the core of future semiconductor design and manufacturing. The Device Scaling technical presentations explore the technologies that enable continued progress along the Moore’s Law curve:
- Advanced Processes and Materials for New Devices: Higher performance demands drive the incorporation of new devices and technologies into semiconductor manufacturing. The new devices require new materials like high-k gate and capacitor dielectrics, low-k interlayer dielectrics, and engineered substrates. Device makers, equipment manufacturers and materials suppliers describe how they integrate these new technologies into production in these presentation slides (click here).
- Lithography for 22nm: The 22nm node will represent a major inflection point for lithography in manufacturing. Many believe that the 22nm node may have to rely on 193nm water immersion lithography with potentially design invasive resolution enhancement techniques. Industry luminaries share their views on the technical feasibility and financial viability of a patterning solution for 22nm. To view these slides, click here.
- Advances in Device Manufacturing: The shift to consumer electronics has forced device manufacturers to focus on fab agility and productivity. The use of new devices and materials has increased the need for new metrology and process control solutions. The rising cost of energy, water and process materials makes conservation and sustainability even more important. TO see how the industry is responding to these new requirements, click here.
- Materials and Equipment Challenges for 32nm and 22nm Devices: What will replace classical CMOS in the next 5 to 8 years as traditional scaling runs out of gas? To look at current R&D efforts to develop the new devices, materials and technologies needed to support the demand for increased performance, view these presentation slides by clicking here.
- Design for Manufacturing: Process technology zooms towards the 32nm and 22nm nodes. This will provide a tremendous benefit in packing additional differentiating functionality into a smaller die, which utilizes lower power. To benefit, the chips must be “manufacturable.” The EDA community and the manufacturing community discuss how to achieve manufacturability signoff before committing designs to silicon in these presentation slides (click here).
Test, Assembly and Packaging TechXPOT
As consumer products become the driving force in the semiconductor industry, demands in device complexity, reductions in size, and lower price pressure have all increased throughout the back-end of the manufacturing process. Both the Test and Packaging industries are developing innovative solutions to address these critical issues:
- Yield Management: As chip complexity grows and device ASPs continue to shrink, maximizing the profitability of a test operation becomes more challenging. The efficient operation of test equipment and management of test results to optimize yield and productivity are pivotal, as seen in the presentations (click here).
- High-Density Packaging: The increasing demand for greater packaging densities poses numerous technical and economic challenges. Technical issues continue to be concerns as flip-chip, wafer-level packaging, and 3D solutions grow in density, with cost always a concern when developing practical solutions. View the slides by clicking here.
- Emerging Technology in Wafer Level Packaging: The consumer device market continues to demand thinner, smaller, and lighter semiconductor packages. Wafer-level packaging (WLP) promises to meet these demands without sacrificing performance. Can the industry address all of these size demands as well as the connectivity of these multi-die (stacked) packages? See what the experts say— by clicking here.
- Testing Increased Functional Complexity: More and more semiconductor packages contain multiple die with a combination of functions. Typically these packages have some mix of logic, analog and memory. View the challenges and strategies of testing these complex packages by clicking here.
- On the Test Floor: Testing challenges continue to arise at both Wafer sort and Final test. Many of these challenges arise from new materials (copper, low-K, etc.), shrinking die and the associated compression of pad pitches, as well as tester to device-under-test (DUT) connectivity. View the slides by clicking here.