32 nm Trends, Technologies and Challenges a Major Focus at SEMI Technology Symposium 2008
32 nm Trends, Technologies and Challenges a Major Focus at
SEMI Technology Symposium 2008
Symposium to be held December 3-5, 2008 at the Makuhari Messe in Chiba, Japan; Registration now Open
TOKYO, Japan-October 13, 2008 - SEMI will hold the annual SEMI Technology Symposium (STS) 2008, December 3-5, 2008 at the International Conference Hall, Makuhari Messe, in Chiba. A major focus of this year’s event will be the development of new technologies for the upcoming 32 nm process node, which is expected to be implemented as early as 2009 for some companies.
The STS is the largest symposium offered by SEMI, and is held in conjunction with SEMICON Japan every December. The symposium provides a collaborative forum that brings device manufacturers and equipment and materials suppliers together to discuss challenges and perspectives of relevant technology trends. This year’s event features ten sessions focusing on new technologies to enable next-generation processes. STS 2007 was comprised of ten technical sessions with 110 seminars, in addition to a keynote speech, and it hosted 2,491 visitors.
Registration for STS 2008 is currently available at our Web site at www.semiconjapan.org. Inquiries regarding STS 2008 will be answered at SEMI Japan Events Registration (Tel: 81-3-3222-5993 or Email: firstname.lastname@example.org).
SEMI is the global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. SEMI member companies are the engine of the future, enabling smarter, faster and more economical products that improve our lives. Since 1970, SEMI has been committed to helping members grow more profitably, create new markets and meet common industry challenges. SEMI maintains offices in Austin, Beijing, Brussels, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.
SEMI Technology Symposium (STS) 2008 at a glance:
- Session: December 3-5, 2008
- Venue: The International Conference Hall in Makuhari Messe (Chiba City)
- Sponsor: SEMI
- Program Chairman: Hiroichi Kawahira, the STS 2008 program chairman and General Manager at Sony
- Registration: Available from October 1, at the SEMICON Japan 2008 Web site: http://www.semiconjapan.org
Session 1: Special Program
Next Generation Energy Devices - Key semiconductor technologies to tackle global warming with: solar cells, energy-saving LEDs and SiC power devices -
In response to soaring worldwide crude oil prices over the past year, and the intensive discussions on the global warming at Hokkaido Toyako Summit held in July 2008, the industry currently faces heightened expectations for technology development in such fields as energy conservation and alternative energy sources. With regard to the technologies relating to semiconductor devices, in particular, aggressive efforts are being made to achieve a breakthrough in device performance by introducing new materials and to accelerate penetration of innovative semiconductor devices. STS Special Session will focus on solar cells, energy-saving LEDs and SiC power devices, all of which currently attract the most attention, and present updated information on their developments.
Microsystems/MEMS - New developments of MEMS business and MEMS equipment -
MEMS is widely recognized as a new industry, and its applications have been expanded from automobiles to consumer electronics and mobile devices. As a result, MEMS has become a common technology to provide innovative functionality. In the business aspect, however, price competition gets increasingly fierce, as typically seen in sensor business, and thereby MEMS growth momentum slightly slows down although the market size increases steadily. In this session, MEMS companies will present how to achieve a breakthrough from the viewpoints of both device and tool.
Inspection & Metrology - Key technology trend of inspection & metrology for the 32 nm hp node -
Development of devices in the 32 nm hp node has started in full swing. In the 32 nm hp node, because of advanced complexity in device structure and shrink in device geometry, marginal changes and variations in profiles will have by far greater impacts on device characteristics than the previous technology nodes. Accordingly, wafer inspection & metrology is expected to play an increasingly important role, and their technical hurdles are getting higher year by year. In response to such technology trends, Inspection & Metrology Session is established again this year. In this Session, experts from public research institutes, device vendors and equipment vendors will first explicate specific requirements for inspection and metrology from the standpoint of device performance realization. Then researchers engaged in the study of leading-edge inspection and metrology will present current status and future challenges of their research and development activities.
Etching - Ultrafine etching technology for the 32 nm node – Combination of profile variability control and metrology -
For devices of the 32 nm node and beyond, etching profile and variability will have much greater impacts on device characteristics. At the same time, a highly advanced metrology will become essential to measure nanometer-order change and variation in profiles and to measure and control fluctuation of etching plasma. Focusing on high-precision profile and variability control in etching process, this session will highlight the need for combination of profile control and metrology. Specifically we will discuss impacts of profile variation on device characteristics, leading-edge profile metrology and plasma metrology. As an example of the demanding etching process in which high-precision profile control is very hard to be realized, we will touch on etching profile control of low-k ILD and HARC (high aspect ratio contact).
Multi-Level Interconnection -The future of next-generation highly-reliable interconnects with the innovation of new materials and structures –
Requirements for the multi-level interconnection technology are as follows: 1) to develop highly reliable process with scaling (More Moore technology) and 2) to develop technology options without scaling (More than Moore technology). To address the above requirements, we will overview the interconnect technologies for 32 nm and beyond, i.e. technology trends and innovative technologies to overcome these challenges. After the overviews, we will discuss the three technologies, namely metallization, dielectric film and CMP, from the viewpoint of the material engineering and the reliability engineering in particular. With regard to the next-generation interconnection technology, this session will present current effort and a future direction of research for both new materials (CNT: carbon nanotube) and new structures (3D packaging). We are planning to ask leading experts of different fields to present the latest R&D efforts to link a fundamental research and a practical research.
DFM/Mask - Mask technologies for 32 nm and beyond – From optical extension to NGL -
This session is designed to overview the technology trends surrounding next-generation mask technologies. Looking toward up-coming developments in lithography technologies, the session will present details about DPT (double patterning technology), which is considered as a prime choice for ArF lithography extension, CL (computational lithography) and DFM (design for manufacturability) as well as their effects on mask technologies. With regard to NGL (next-generation lithography), the session will highlight EUVL (extreme UV lithography) and NIL (nano-imprint lithography) and introduce their on-going development efforts including some consortia initiatives. The session will also present the latest trends of infrastructure technologies essential for realization of next-generation masks, such as mask material, mask writing equipment, mask inspection equipment and mask repair equipment.
Testing - Breakthrough of testing technology – From innovation to confidence -
Through the adoption of the DSM (deep submicron) process, the density of IC devices has increased significantly enough to build a system in a chip. In order to test such high-density IC devices, it is necessary to merge conventional testing technologies which were originally developed by purpose (DFT, diagnosis/analysis, metrology etc.) and then evolve them into an upper-level comprehensive technology. In this session, experts who are active in the front lines of testing technology development will present the latest R&D achievements and technology trends.
Advanced Device - 32nm/22nm node device and process technology -
For advanced devices of the 32nm/22nm node coming after the 45nm node which is about to be in volume-production phase, it will become increasingly difficult to achieve required device performance and control variability while keep shrinking device geometry. In an attempt to overcome this challenge, high-k dielectric film, metal gate electrode, 3D fin structure, Ge-MOS etc. are actively developed. In parallel, memory technology to realize stable device characteristics in the 32nm/22nm node is being developed. In this session, prominent engineers will present advanced device and process technologies.
Lithography - Explore the future of immersion lithography and beyond -
Lithography technology is reaching a new milestone as high-NA immersion lithography tool featuring NA of 1.30 or higher started being put in operation. Development as a simple extension of the conventional lithography technologies has been ceased while a comprehensive technology, such as double patterning technology which combines etching process and lithography closely, becomes promising. Meanwhile on-going advancements of NGL (next-generation lithography) are drawing attentions; e.g. a prototype chip is fabricated with an EUV tool. This session will overview the current status of the lithography technology that becomes increasingly complex through the integration of neighboring technologies, and discuss its future developments.
Packaging - Wafer level vs. Package level – Which will play a leading role in diversified 3D technologies? -
Jisso technology has presented solutions to realize various requirements for electronic devices, such as higher performance, smaller size and lighter weight. An ultimate achievement of its kind is commercialization of electronic devices adopting wafer-level 3D packaging. Meanwhile POP (package-on-package) technology, a package-level 3D technology based on the existing technology, has also been introduced in volume-production process, and more advanced versions are being proposed. Packaging Session in STS 2008 will focus on wafer-level packaging and package-level packaging, and closely examine which will play a leading role in the future Jisso technology. In the morning and afternoon panel discussion sessions, we will discuss the two technologies separately so as to identify potential challenges of each technology.
Programs Division, SEMI Japan
Scott Smith, SEMI US
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