Fab Automation Evolving in Gigafab Era


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Fab Automation Evolving in Gigafab Era

by David Lammers

With a flurry of new fabs under construction following the recent downturn, fab automation vendors and chip manufacturers have an opportunity to move to higher levels of automation.

For foundries, the new fabs under construction in Taiwan, New York, Austin, and elsewhere provide the opportunity to add Automated Reticle Handling Systems (ARHS) to complement the wafer-handling AMHS. Tom Sonderman, vice president of manufacturing systems and technology at GLOBALFOUNDRIES, said Fab 8, now under construction in Malta, N.Y., will feature scheduling and dispatching capabilities which support automated reticle handling. “For foundries which have many different reticle sets,” Sonderman said, “getting the reticle to the tool at the exact right moment is key to fab productivity.” Fab 8 will be “fully ARHS capable,” Sonderman said.

Zero-footprint storage is another priority. The GLOBALFOUNDRIES Fab 1 in Dresden, Germany has about 100 wafer stockers, while the goal for Fab 8 is 20. Another emphasis will be on priority lots, Sonderman said, with “some wafers moving at different velocities.” Priority lots might gain a ‘Super Rocket’ designation for expedited processing. The dispatching tools will need to perform real-time dispatching, and the fab will need to be configured to support a faster processing flow for critical lots.

One opportunity is to more fully implement the improved Interface A equipment data acquisition standard. Some chip vendors have shied away from the additional cost of several tens of thousands of dollars per tool, which can quickly add up when many dozens of new tools are purchased with the additional interface. Marlin Shopbell, Next Generation Factory project manager at Sematech’s ISMI subsidiary, argues that semiconductor companies are spending too much time and money to set up new tools. The setup process could be simplified by asking a tool for the metadata possible with the SEMI Interface A, Shopbell said.

A transition from 300 mm to 450 mm wafers would impact wafer handling and other automation standards. (Source: Sematech ISMI)

 

For SECS/GEM, the ability to foolproof process recipes proved to be such a critical advantage that SECS/GEM achieved widespread adoption, making recipe blunders a thing of the past. “Perhaps the industry is still searching for that critical application that makes Interface A absolutely necessary for everyone,” Shopbell said.

Semiconductor manufacturers will need to pay more attention to scheduling and dispatching as leading-edge chips require more process steps. With some chips requiring 500 to 700 process steps and larger mask sets, keeping cycle times relatively constant will require improved scheduling. Shopbell said.

The added complexity is leading semiconductor companies to implement high-level fab management tools from commercial automation vendors, or maintain internal automation and equipment engineering solutions themselves.

With chip demand booming again, the large IC manufacturers appear to be persevering in their coordinated effort to develop a 450 mm wafer toolset. The SEMI standards for FOUPs, wafer handling, and other automation elements are falling into place. Sematech’s ISMI program is in transition, moving from Austin to the Albany CNSE campus over the next 6 to 9 months, with a larger cleanroom available. Proposals to the New York state legislature for subsidies for a 450 mm equipment development effort are now being considered. And the “IST” IC vendors backing the 450 mm transition, including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing Co. Ltd., are being asked to pony up funding for the 450 mm development line planned for Albany Nanotech. IMEC, in Leuven, Belgium, also has a new clean room that could be used for 450 mm process development.

The CNSE complex at the University of Albany is likely to be the new home for Sematech’s 450 mm development program by next year. (Source: Sematech ISMI)

 
 

In one sense, all of the automation advances being implemented for the next-generation 300 mm fabs can easily be ported to 450 mm fabs which might be built several years from now, or later in the decade. But if the key stakeholders backing the 450 mm transition push ahead with financial support for 450 mm development efforts, it will indicate that these manufacturers anticipate another leap in the economies of scale driving NAND, DRAM, MPU, and consumer SoC production. That would have major impacts on how gigafabs are automated and managed, no matter what the wafer size.