Keynote Preview: Today’s Research for the Next Decade
Presenting on the Keynote Stage at SEMICON West, Paolo Gargini, Intel Fellow and ITRS chairman, will explain the importance of the pipeline from research to high volume, and its role in equivalent scaling development.
by Aaron Hand
The CMOS process is undergoing a complete renovation that will further differentiate those companies that have developed an efficient pipeline to bridge from risk research to high-volume manufacturing. So says Paolo Gargini, Intel Fellow, director of technology strategy at Intel Corp., and chairman of the International Technology Roadmap for Semiconductors (ITRS), who will present a Wednesday keynote at SEMICON West (http://www.semiconwest.org/SessionsEvents/Keynotes/ctr_036167) about the newest phase of semiconductor manufacturing — equivalent scaling.
As long as targeted research is initiated well ahead of when it is required in development and manufacturing, the industry can find the equivalent scaling solutions it needs to stay on track. The pipeline from research to high-volume manufacturing takes as much as 10 years, however, so planning and systematic execution is essential, Gargini says.
For example, research initiated on strained silicon in the early 1990s went into manufacturing in the early 2000s, and research on high-k/metal gates in the mid-1990s went into manufacturing shortly after the mid-2000s. “I am confident that among the many possible solutions already demonstrated in research, we will continue to extract and introduce into manufacturing the next elements of equivalent scaling in a timely fashion,” says Gargini.
To that end, fundamental research has substantially increased. But it is no longer the domain of corporations, as it has shifted instead to universities, consortia, institutes and national labs. “Nowadays corporations are under pressure to optimize return on investment,” Gargini notes. “Universities offer a very cost-effective way of conducting fundamental research on high-risk items.”
For any given research case, companies are able to select the most qualified universities on a given subject, immediately access the expertise, and substantially reduce the time required to reach a fundamental understanding of subjects that may normally be outside the typical expertise of the corporation. At that point, consortia are useful to test the ideas in a pre-competitive environment. “Eventually, each partner company must do its own R&D work to adapt the best ideas to its product and manufacturing environment, and to differentiate its process technology for best competitive advantage,” Gargini adds.
According to Gargini, new device studies and process evaluations generated by the new approach have reached “unprecedented levels,” and have produced a new set of researchers from fundamental physicists to chemists and material scientists.
Asked about some of the most innovative solutions that MOS technology has seen over the years, Gargini pointed to silicon-germanium PMOS strained silicon, which made its debut in 2003. “This technology dramatically increased p-channel mobility, hence making it more efficient,” he said. In 2007, the introduction of high-k/metal gate (HKMG) reduced leakage by more than 100 times, he added. “HKMG is the most fundamental change to the basic MOS transistor that the industry has seen in over four decades.”
Looking further back, Gargini includes chemical mechanical planarization (CMP) and the introduction of the excimer laser as a lithography light source as important innovations, as well. With an eye to the future, Gargini notes the considerable effort going into introducing germanium and III-V compounds into the CMOS process, multiple examples of which will enable further reduction of power consumption. “What is most relevant is that these new materials can be grown on top of silicon wafers and therefore can be integrated into the mainstream silicon technology with only minor modifications to it,” he says.
A key challenge, however, will be developing cost-effective high-volume manufacturing equipment solutions to integrate the materials into the CMOS process flow, Gargini says.
Paolo Gargini’s keynote speech, “Welcome to the Next Decade”, will be presented on Wednesday, July 14, from 10:45 am to 11:30 am at the Keynote Stage, Esplanade Hall, Moscone South