Perspectives on 450mm

Perspectives on 450mm

The transition to manufacturing semiconductors on larger wafers continues to be one of the hottest topics around SEMICON West.  Some chipmakers have committed to advancing the transition. Intel announced that its D1X fab in Oregon will be 450mm compatible (2013). TSMC announced a 450mm pilot line by 2013-2014. IMEC and ISMI have well-established programs focused on the challenges posed by manufacturing with 450mm wafers and the University of Albany's College of Nanoscale Science and Engineering (CNSE) is expanding facilities to encompass 450 program R&D.


New Tools: Before OEMs can start developing IC fabrication tools, the wafer manufacturers need the capabilities to produce the substrates needed for process development and integration.  At SEMICON West, several new tools were announced for the production of bulk silicon and SOI wafers, including KLA-Tencor’s 450mm unpatterned wafer inspection system (Surfscan SP3).  In addition, EV Group unveiled the first bonding system for 450mm wafers manufactured from SOI substrates (EVG950SOI/450 mm).    


450 panel at SEMICON West 2011
SEMICON West 2011 450mm Panel (from left): Paolo Gargini (Intel), Thomas Sonderman (GLOBALFOUNDRIES), Bob Johnson (Gardner), Hans Lebon (imec), Brian Trafas (KLA-Tencor), David Hemker (Lam); moderated by Pete Singer (Pennwell Electronics Manufacturing Group).

With increasing interest in a near-term 450mm pilot line development, many critical elements need coordination for affordable high-volume 450 manufacturing to occur.  At the recent SEMICON West 450 Wafer Transition Forum, panelists from throughout the supply chain grappled with the numerous issues involved.  Here’s a brief summary of panelist presentations:


Intel: Paolo Gargini, ITRS chairman, IEEE and Intel Fellow, entitled his presentation “Phase 1.”  He discussed the amount of silicon used and pointed out the resiliency of the industry with a dip in 2001 and in 2009. The number of transistors shipped per year has increased about 40% per year, with the average transistor price dropping every year.

Paolo GarginiWith the cost of a leading-edge fab continuing to rise (Fab $6.0 billion; Pilot Line $1-2 billion; R&D Process $0.5-1.0 billion), Gargini said that the number of companies “in the game” starts to shrink and there’s only 8-10 companies (Intel, Samsung, TSMC, TI, Toshiba, Renesas, ST, Hynix, Micron) that can afford to be in the game with 15 others somehow staying in the game (Qualcomm, Elpida, Infineon, etc.).  (Data Source: McClean Report, 2011).

 

 

 

Sonderman Photo

GLOBALFOUNDRIES: Thomas Sonderman, VP of Manufacturing Technology at GLOBALFOUNDRIES, in a presentation entitled “"Reaping the Benefits of the 450mm Transition," focused in on a comprehensive 450mm cost model (see Figure 1).  “We’re getting to the point where it costs more and more money to make these transitions and there’s a real need to make sure that when we do it, we do it right as an industry.”  He continued, “Clearly there is a value to doing this; the challenge is going to be “how do you do it? What’s the mechanism to drive collaboration? A few companies will get together work together and synergize as a fab community so that we’re working with the supplier community to make sure we’re all in synch as we go down this path. He presented this cost model (Figure 1).

 

Figure 1: Comprehensive 450mm Cost Model
450mm Cost Model


Sonderman also discussed how the economics of 450mm are most pronounced at lower nodes:

  • A 450mm fab with a capacity of 40-45k wafer starts per month can produce the same volume of die as a 300mm fab with 100k wafer starts per month.
  • A 40k 450mm wafer fab requires ~25% less CapEx than a 100k 300mm fab with equivalent number of die output (22nm node)
  • Model indicates approximately 10-15% savings in cost per die for 32nm processes, with savings reaching 20-25% for 22nm node
  • Savings are more prominent for lower nodes since the equipment share of overall costs/die are higher
  • Source: IC Knowledge Wafer cost and pricing model, inputs from interviews with IC Knowledge, CNSE, and PDF Solutions

He also discussed the challenge of dealing with a wafer transition while also dealing with getting ready to make a major lithography transition towards EUV, a real enabler for our 14nm and below technologies.
Sonderman stated that there’s clearly a benefit to making the transition, but he also said, “Until you get the litho community to get behind such a transition, and they are actually going to start making patterning cells and patterning tools that we can then begin to build the process… you really have to question when things are going to happen. Right now the lithography community is focused on EUV.”


He summarized by talking about how the 300mm transition led to significant benefits for leading players, with a greater than 30% cost savings over 200 mm, driven by increased capital efficiencies.  He noted that significant headroom still exists in 300mm but that the 450mm transition is inevitable because the transition has the potential to generate significant cost savings— about 25% less CapEx and as much as 20-25% savings in cost per die at 22nm.  He stressed that must work still needs to be done, working collaboratively through industry consortia to enable an effective transition to 450.


Gardner: Bob Johnson, Research VP at Gardner, took on the topic, “"450mm: It's All about Economics," and discussed how periodic wafer size increases are needed to compensate for more expensive nodes, and that the transition to 450mm is expected to save 30% on production costs. Johnson noted that 450mm has “nothing to do with Moore’s Law— it’s purely a cost play.”  He continued, “When you look at it from the perspective of the semiconductor manufacturer, it’s really quite simple, cheaper equipment and production costs for the same incremental output. They save money…primarily in capital equipment. When you look at it from the equipment manufacturer side, you’ve got a really good question. We’ve got the opportunity to spend billions of dollars on R&D that could go for other projects and end up cutting our market by about 30% going forward.”  He said, “450mm creates a fundamental conflict of interest between the semiconductor and equipment manufacturers and this conflict of interest has to be resolved if we’re going to go forward.”  

Bob Johnson Image Johnson said, “When 450 comes into production, we’re going to be at the 14 or 10nm or below technologies… that means we need EUV, we need immersion for mix and match and we probably need dry litho, all, to be economically viable. And then we ask, how many nodes do we have?  How long is conventional silicon going to be able to keep going from the 10nm level…”
He discussed the R&D ROI considerations (see Figure 2).

 

 

 

Figure 2: R&D ROI Considerations

 

300mm -- 1997

450mm -- 2011

Industry Growth

17%/yr CAGR

~6%/yr CAGR

# of Nodes

10+

3?4?

# of companies who can afford fabs

~25

<10

Who pays for R&D

Equipment Companies

?

Source: Gardner

Johnson also rebutted some 450mm “myths” including, “450mm fabs will cost much more than 300mm fabs.”  He says that the reality is that 450mm will cost less per unit output than 300mm.  Another myth is  “450mm will reduce the number of companies who can build fabs.” He said that the reality is that 300mm fabs have already done that.  Less than ten companies are currently building leading-edge fabs and the 450mm will make it easier to stay in the game because it’s cheaper.


He recommends: the development of industry-wide targets, milestones, and timetable—agreed upon by both semiconductor and equipment manufacturers; identifying specific target nodes for performance demonstrations; a willingness to stop if agreed upon cost targets are not met; and making sure that it makes economic sense for all involved.  

Lebon Image Imec: Hans Lebon, VP Fab & Process Step R&D&M Technology at imec, discussed "Role of an R&D Consortium, Imec, in a Cost Effective 450mm Migration," discussed Traditional rate of cost reduction per transistor cannot be maintained without a wafer scale-up.  So far, the semiconductor industry has been able to increase wafer size about once every 10 years.”
He explored how to keep 450mm migration costs under control by applying what we learned from the 300mm migration. He focused on the role of R&D consortia in the process (see Figure 3).

 

Figure 3: Role of R&D Consortia
R&D Consortia


Lebon concluded that 450 will become reality and that the “pilot could happen in 2015-16.”

KLA-Tencor: Brian Trafas, CMO at KLA-Tencor, presentation was title “The Importance of Process Control at 450mm.” He said, “What we see as some of the key challenges that we identified at 300mm that we as well see as challenges at 450mm. Clearly, there’s a productivity play, there’s a cost reduction in going to 450mm, we’re seeing more and more drive and transparency around 450. I think that the industry has been betting on EUV and we need EUV to be successful.  I think that we need that type of level of funding as well and transparency for 450 to be successful. Some of the challenges to date as an equipment manufacturer have been what is the design node, what is the timing, when should I start to invest….  This will be an advanced node— less than 14nm, and as such, the products we’re building today are not going to be relevant for those types of capabilities. So the question is, when is the timing for us to do the R&D?  More transparency is necessary for us to be successful in moving forward with 450.”

Brian Trafas Image Addressing the main 450mm “drivers,” Trafas noted these:

  • Increased Productivity: more die yielded per wafer at similar 300mm yields
  • To help alleviate rising costs of producing future advanced technology nodes; more chip density per wafer
  • Strong support and funding by industry leaders critical for success

 

 

Trafas also talked about how process control is critical for 450mm success (Figure 4) and the challenges for equipment suppliers (Figure 5):

 

Figure 4: Process Control Critical for 450mm Success
450mm Success image

In terms of challenges for equipment suppliers, Trafas mentioned two key challenges:

  • Beam Scanning Tools:  Slower throughputs as wafer size increases; Innovation, scanning speed and other improvements needed
  • Area Based Tools: Within wafer uniformity is big challenge; Center to edge variations increase; Multi-zone control critical 

Lam Research: David Hemker, VP of New Product Development at Lam Research, presented on “The 450mm Wafer Transition: An Equipment Supplier's Perspective." Hemker believes that as “traditional” scaling becomes more difficult and costly, a wafer size transition becomes inevitable. For 450mm, the transition has started.”  He said that the real questions are: “How much?” and “How Quickly?”  He illustrated the potential risk of a timing disconnect between customers and suppliers, with the potential risk of additional costs if expectations and plans are not carefully coordinated.  In addition, he focused on potential equipment scaling issues that need to be addressed during the development phase:


Hemker Image

  • Scaling of plasma tools (Etch, CVD, PVD, Plasma Implant, …) is straightforward but there are cost implications: Plasma and gas densities scale with chamber volume not wafer radius; Plasma flux scales with the wafer area; At best it will be an x2 increase with a simple scale-up – at worst an x3 increase (applies to power generators and vacuum pumps)
  • Equipment Scaling Issues—RF Power and Pumping: Not only do the amount of RF power and pumping required for 450 mm increase non-linearly, but the incremental cost for that additional capability also increases non-linearly. RF generator $/W increases non-linearly with higher power.  These costs will likely come down over time. Turbo pump $/cfm show similar behavior with higher flows.

 

Hemker summarized by saying that Lam will have 450mm equipment sets ready when customers need them.
As the global supply chain deals with wafer size transition, pre-competitive collaboration will continue to be the best path towards economic efficiency and industry rationality, and Standards play a major role.

While uncertainly about development funding remains, SEMI Standards task forces are working on  encouraging the industry to collaborate on key issues like the technical parameters for 450mm silicon wafers, physical interfaces, carriers, assembly and packaging. To date, SEMI has 10 task forces working on 450 and has published seven 450mm standards with 13 more in the pipeline.


For information on SEMI, visit www.semi.org. For a recent executive viewpoint on 450mm, visit www.semi.org/en/node/38856.   For information on SEMI Standards, please visit www.semi.org/en/Standards or contact James Amano at jamano@semi.org.

September 8, 2011