CGMG General Meeting at TechXpot Revealed Future Trends for Semiconductor Materials
SEMICON West 2012 CGMG Meeting Summary
by L. Shon-Roy, Techcet Group
SEMICON West, San Francisco, July 10, 2012: The Chemical and Gases Manufacturers Group (CGMG) Meeting this year at SEMICON West provided powerful information on Future Trends of Semiconductor Materials. The event featured LED high-efficiency technology presented by Christian Wetzel, Ph.D. of Rensselaer Polytechnic Institute University (RPI), and Development Work on next-generation semiconductor devices (sub 22nm node) by Paul Kirsch, Ph.D., director of Front End Processes at SEMATECH. The event was rounded out by a presentation on the materials markets by Mark Thirsk of Linx Consulting and a panel discussion moderated by Lita Shon-Roy of Techcet Group, an Electronic Materials trends and market analysis consulting firm.
Dr. Wetzel presented new development work on higher efficiency lighting and power device technology, “Energy efficiency and green technology with wide bandgap GaN-based epitaxy”, explaining that most of the energy of current LED’s is lost to heat through the back of the LED and/or imparted to the phosphor needed to provide the color or shade of lighting desired. The technology RPI is working on would lessen the dependency on phosphors, optimizing the wavelength of the LED light emitted as well as the efficiency of the LED itself.
Dr. Kirsch presented Sematech’s development of sub 22nm device technologies, “Extending CMOS with III-V on Si: Simultaneous low power and high performance” focused on germanium and III-V (i.e. InGaAs) substrates. New processes will be required for doping these substrate materials which must uniformly dope high aspect ratio (3D) structures. In addition, compatible cleaning and etching technologies will have to be developed. The road map presented showed silicon n-MOS and SiGe pMOS for 14nm CMOS, and a combination of Ge and/or III-V gates for technology nodes at 10nm and below. Several challenges to growing these materials on silicon can be solved by adjustment in trench depths and process optimization. The Sematech research showed plasma junction doping methods being successfully employed, as opposed to ion implant, for 11nm devices.
Mark Thirsk presented an overview of semiconductor device trends “The Development of the Semiconductor CVD and ALD Requirement.” He presented wafer starts by technology node, indicating that metal gates will be fully employed at the 14/15nm node. Memory and Logic scenarios for device technology changes were presented. Precursors families for various technologies were also discussed.
For more details and to review these presentations, please go to: http://www.semiconwest.org/node/8476
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