ASMC 2013 - Schedule

ASMC 2013

Conference Highlights  (Download Complete ASMC 2013 Schedule)

Keynotes   
Tuesday, May 14, 2013:
Assessing the Threats to Semiconductor Growth: Technology Limitations versus Economic Realities

Subramani Kengeri

Vice President, Advanced Technology Architecture, Office of CTO
GLOBALFOUNDRIES

(sponsored by CNW)
  Subramani Kengeri
Wednesday, May 15, 2013:
Fab Materials Next Generation Challenges: Affordability & Quality
Tim Hendry, Vice President, Technology and Manufacturing Group

Intel Corporation
(sponsored by CNW)
  Tim Hendry
Thursday, May 16, 2013:
IC Market Trends and Forecast
Bill McClean, President

IC Insights
  Bill McClean

Tutorials:
Computational Lithography
: Vivek Singh, Fellow, Intel Corporation (Tuesday, May 14, 2013)
3D/IC: Sarasvathi Thangaraju, Package Technology and Integration Group, GLOBALFOUNDRIES (Thursday, May 16, 2013)

May 15, 2013
Panel Discussion: Super Size Me!
  (sponsored by DAS Environmental Experts)
450 mm wafers, along with the equipment to handle, measure, and process them, are topics of discussion and development within the semiconductor industry.  Per Paul Farrar, general manager of G450C, not much will change in the process. However, while 300 mm fabs brought a major transition from manual transport of wafer cassettes to automated transport of fully enclosed pods, the demands of the heavier wafers and the cleaner process environment they require will still drive added facilities and equipment challenges.  And while the basic automation and handling model is unlikely to change, how will the industry handle the process and economic challenges raised by the next wafer size?  These and other issues related to 450 mm will be discussed by panelists at ASMC 2013.

Moderator: Paul Farrar, Director, G450C
Panelists:
Kirk Hasserjian, Corporate Vice President, SSG, Applied Materials
Dr. Brian Trafas, Chief Marketing Officer, KLA-Tencor
Mark Fissel, Vice President, 450 mm Program, Lam Research
Dr. John  Lin, Director of 450mm Project, TSMC
 

Networking Receptions
Welcome reception (sponsored by Applied Materials) and pre-registration.  (May 13, 2013)
Poster reception, in conjunction with interactive poster session (sponsored by KLA-Tencor, NY Loves Nanotech; Marcy Nanocenter) May 14, 2013
GLOBALFOUNDRIES Reception (sponsored by GLOBALFOUNDRIES, Saratoga Convention & Tourism Bureau; Saratoga Economic Development Corporation).  This reception does not include a tour of Fab 8.  (May 15, 2013)

Technical Sessions

 Tuesday, May 14, 2013  
Session 1: Advanced Patterning/Design for Manufacturing (in parallel with Session 2)
Chairs
: Yayi Wei, GLOBALFOUNDRIES; Jacek Tyminski, Nikon Research

Advanced patterning and design for manufacturing (DFM) are key elements of leading edge semiconductor fabrication. This session covers a broad spectrum of innovations in these areas, including source and mask optimization, carbon nanotubes and improved double patterning.
  Session 2: Factory Optimization I (in parallel with Session 1)
Chairs:
  Scott Lantz, Intel Corporation; Jan Rothe, GLOBALFOUNDRIES

Semiconductor equipment and manufacturing is increasingly complex and driven by strict economic constraints.   It is vital for IC production to improve efficiency and control costs.  This session discusses new approaches to factory optimization based on data analysis and simulation.
Session 3: 3D/TSV Technology (in parallel with Session 4) 
Chairs: Hamid Khorram, Nikon; James Lu, RPI; Thuy Tran-Quinn, IBM
This session will cover key innovation in the field of 3D/Through-silicon via technology (TSV) including TSV processing, interposer, thin-wafer handling, reliability and power delivery.
  Session 4: Factory Optimization II (in parallel with Session 3) 
Chairs: Dave Gross, GLOBALFOUNDRIES; Holly Magoon, Nikon; Patrick Varekamp, IBM
Semiconductor equipment and manufacturing is increasingly complex and driven by strict economic constraints.   It is vital for IC production to improve efficiency, control costs, and be good environmental stewards.  This session covers novel solutions for factory and equipment productivity as well as environmental efficiency.
Session 5:  Interactive Poster Session and Reception (sponsored by KLA-Tencor, NY Loves Nanotech/Marcy Nanocenter)
Chairs:  Thanas Budri; Texas Instruments; Eric Eisenbraun, CNSE; Dan Maynard, IBM; Mike McIntyre; Patrick Varekamp; IBM; Paul Werbaneth
Innovative integrated circuit functionalities continue to be integrated in semiconductor manufacture. This session presents analysis of the effects of enabling technologies, and innovative integrated circuit designs.
Wednesday, May 15, 2013 
Session 6: Yield Enhancement I (in parallel with Session 7) (sponsored by FEI Company)
Chairs: Oliver Patterson, IBM; Gary Green, Alphray

Defect inspection, yield analysis and optimization are integral components in the development and manufacture of semiconductor devices.  This  session covers a variety of techniques to improve yield using design, defect,  electrical  test,  bitmap and failure analysis data.  Using two or more of these data sources together intelligently is a recurrent theme.
  Session 7: Advanced Metrology I (in parallel with Session 6)
(sponsored by Metryx)
Chairs:  Israel Ne’eman, Applied Materials, Alok Vaid, GLOBALFOUNDRIES
This session details some advanced metrology techniques, including new ellipsometry, spectrometry, infra-red, e-beam, X-ray and metrology modeling use cases.
 
Session 8: Defect Inspection I (in parallel with Session 9)
(sponsored by Green Tweed)
Chairs:  Jeff Barnum, KLA-Tencor; Jason Massotti, IBM; Kazunori Nemoto, Hitachi Hi-Tech
Defect inspection, yield analysis and optimization are integral components in the development and manufacture of semiconductor devices.  This session will feature a novel 'virtual' inspection technique, improvements in optical and edge inspection, and defect sampling methodologies to help drive yield.
Session 9: Advanced Equipment Processes and Materials (in parallel with Session 8) 
Chairs: Chris Long, IBM; Brett Williams, ONSemiconductor
Both advanced memory, analog and logic manufacturers face daunting challenges as the next generation device nodes come on line. These challenges are being met by the development and applications of innovations in equipment, materials, and processes. This session will focus on solutions to advanced application requirements and will highlight the latest innovations that are being implemented in leading edge high volume manufacturing.
Session 10: E-Beam Inspection (in parallel with Session 11) 
Chairs: Jennifer Braggin, Entegris; Jeanne P. Bickford, IBM
Defect inspection, yield analysis and optimization are integral components in the development and manufacture of semiconductor devices.  This  session  will feature papers describing how e-beam inspection is used to rapidly drive yield for both physical and voltage contrast defects.
Session 11: APC (in parallel with Session 10) 
Chairs: Agnés Roussy, EMSE; Raymond Van Roijen, IBM
This session covers innovations for advanced process control, including new methods in fault detection and classification (FDC), process controls and virtual metrology for predictive maintenance.
Thursday, May 16, 2013
Session 12: Yield Enhancement II (in parallel with Session 13)
Chairs: Philippe Campion, STMicroelectronics; Amiad Conley, Applied Materials; Larry Pulvirent, GLOBALFOUNDRIES

Defect inspection, yield analysis and optimization are integral components in the development and manufacture of semiconductor devices.  This session covers process engineering work in N2 purge and cleans to minimize defectivity and improve yield.
Session 13: Advanced Metrology II (in parallel with Session 12) 
Chairs: Franz Heider, Infineon; Dick James, Chipworks
This session details some advanced metrology techniques, including new ellipsometry, spectrometry, infra-red, e-beam, X-ray and metrology modeling use cases.
Session 14: Defect Inspection II (in parallel with Session 15)
Chairs: Mike Sevegney, Pall Corp.; Dieter Rathei, DR Yield

Defect inspection, yield analysis and optimization are integral components in the development and manufacture of semiconductor devices.  This session will feature a number of case studies where key technology limiting defect types are characterized and eliminated.  The final paper is a study of the ability of different tools and tool modes to measure the size of defects.
Session 15: Advanced Equipment Processes and Materials (in parallel with Session 14)
Chairs: Naomi Yoshida, Applied Materials; Rob Pearson, Rochester Institute of Technogy

This session provides an overview of the state of advanced memory technology, spin torque magnetic memory and novel processing techniques. The final paper gives insight into the status of volume high-purity carbon nanotube production.