downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Member company iconResource item iconStore item iconGroup 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
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Real Intent’s Prakash Narain on Chip Design and Verification’s ‘Shift-Left’ to Reduce Costs and Cycle Times

Dr. Prakash Narain, president and CEO of Real Intent and a member of the ESD Alliance Governing Council, recently offered insights on the vexing functional verification challenges that consume a significant portion of the chip design cycle.

IBS CEO Handel Jones on the Race to the Future of AI

Handel Jones, a well-known, longtime strategic analyst and commentator covering the semiconductor industry, authored the recently published book – When AI Rules The World: China, the U.S. and the Race to Control a Smart Planet. I spoke with Jones about the fascinating read.

Griffin Securities’ Jay Vleeschhouwer Offers Wall Street View of EDA Industry

Jay Vleeschhouwer, managing director of Griffin Securities, has followed the EDA industry as a leading financial analyst for 25 years and is a popular speaker at the annual Design Automation Conference. Vleeschhouwer discusses his DAC presentation The State of EDA: A View from Wall Street.

Needham & Company Senior Analyst Charles Shi on EDA Powering Through Semiconductor Industry Cycles

Charles Shi, Principal, Senior Analyst, Needham & Company, LLC., recently offered an upbeat assessment of the electronic design automation (EDA), silicon intellectual property (IP) and services industries, or what SEMI refers to as the electronic system design (ESD) ecosystem.

S2C Paves Way to Digital Innovation with Cutting-Edge Chip Design Verification Solutions

Founded in 2004, S2C’s worldwide customer base uses its desktop and enterprise field programmable gate array (FPGA) prototyping tools to verify system on chip (SoC) and application-specific integrated circuit (ASIC) designs will work as intended.

ESD Alliance Combats Piracy

ESD Alliance’s License Management and Anti-Piracy (LMA) Committee has worked with member companies Cadence, Siemens EDA and Synopsys to develop a protocol for use with software license management systems to provide strong protection against piracy by defining how servers can be uniquely identified.

Excellicon – Managing Critical Timing Constraints Across Design and Verification to Reduce Timing and Signal Integrity Issues

Rick Eram, Excellicon’s VP of sales and operations, discusses ways for designers to compare the physical floorplan against the actual register transfer level (RTL) code and constraints, chip design trends and complexity, and a few of his predictions for the design and verification market.

How Synopsys is Transforming the Chip Development Landscape Via the Cloud

Vikram Bhatia, Director of the Synopsys Cloud Go-to-Market and Product Strategy, discusses leveraging a flexible, pay-per-use approach to fuel the next phase of semiconductor innovation - bring your own cloud (BYOC) and software as a service (SaaS) deployment model.

Methodics by Perforce Surveys Semiconductor Design Professionals on Product Lifecycle Management

Product lifecycle management is a well-adopted methodology used in mechanical design. Until recently, it was not widely used in the semiconductor industry. That all changed when Methodics created intellectual property lifecycle management for tracking and analysis of semiconductor IP and design.

Semiconductor Manufacturing, Supply Chain Challenges and Startups in France: Aselta Weighs in

The increasing complexity of IC manufacturing poses a number of challenges including the mask data preparation required to enable technology improvements such as multi-beam (MB) mask writers and extreme ultraviolet (EUV) lithography. Thiago Figueiro, VP of Sales & Marketing of Aselta weighs in.