SiC—Silicon Carbide Webinar #6

SiC—Silicon Carbide Webinar #6: Basal Plane Dislocation Defects and the Impact on Device Performance

Silicon carbide (SiC) chips are displacing their incumbent silicon counterparts in several high-volume power applications. As SiC market share continues to grow, the industry is lifting remaining barriers to mass commercialization including the higher-than-silicon chip cost that increases disproportionately with area, defects that limit chip yield and area, reliability and ruggedness concerns, and the need for a trained workforce to skillfully insert SiC into power electronics circuits.

With respect to fabrication, the SiC industry is successfully leveraging the fully depreciated legacy silicon fab infrastructure and is making the relatively small financial investments that allow mature silicon fabs to process SiC. A key aspect of cost-effective fabrication is limiting defects that degrade device performance and compromise yields. Over the past twenty years, significant progress has been made in improving SiC material quality, and Basal-Plane-Dislocations (BPDs) are the last major catastrophic defect. In this presentation, I will discuss how bipolar-current induced electron-hole pair recombination at basal plane dislocations generates stacking fault (SF) formation and expansion, which degrade on-state current conduction. I will present and interpret experimental data of several transistors that exhibit severe BPD related electrical degradation, and of others that demonstrate “intermediate” or no degradation at all. For impacted transistors, I will identify and analyze the electrical characteristics that exhibit degradation as well as those that remain unaffected under bipolar stress. Finally, I will show that BPD related degradation is fully reversed by high temperature annealing, and the transistor returns to its original “undamaged” operational state.

View other webinars in the SiC Series

• Webinar #1—Silicon Carbide Material Properties, Key Applications, and Fabrication Basics: Making the Transition from Silicon
• Webinar #2—Non-CMOS Compatible SiC Power Device Fabrication in Volume Si Fabs
• Webinar #3—Bidirectional SiC and GaN Switch Technology 
• Webinar #4—Understanding SiC Chip Cost, the Impact of Defects, and the Case of Price Parity with Si at the System Level 
• Webinar #5—SiC Edge Termination Technology

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