downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Member company iconResource item iconStore item iconGroup 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
Skip to main content

Pact for Skills: X-FAB on Opportunities for Europe's Semiconductor Industry Growth

The Pact for Skills aims to support upskilling and reskilling and generate European, national and regional funding to attract new talent. Launched by commissioners Breton and Schmit, the Pact makes it a priority to create a well-skilled workforce in microelectronics R&D, design, and manufacturing.

Open Platforms are the Foundation for Advanced System Design

A critical foundation for success in this new multiphysics reality is the development of open, extensible and cloud-optimized platforms that enable many different tools and data sets to work together and build towards a realistic and accurate simulation of physical reality.

Methodics by Perforce Surveys Semiconductor Design Professionals on Product Lifecycle Management

Product lifecycle management is a well-adopted methodology used in mechanical design. Until recently, it was not widely used in the semiconductor industry. That all changed when Methodics created intellectual property lifecycle management for tracking and analysis of semiconductor IP and design.

3D-IC: Great Opportunities, Great Challenges

Electronic designers demand greater integration densities and faster data transfer rates to meet the growing performance requirements of AI/ML, 5G/6G networks and autonomous vehicles as these technologies have outpaced the capabilities of any single chip.

Electrostatic Energy Drives Higher Power-Efficiency and Performance in Chip Design

Azeez Bhavnagarwala, Metis’ founder and CEO, speaks about advanced CMOS Memory and Arithmetic component intellectual property (IP) to improve energy efficiency and performance of processors.

Conquering 2.5D and 3D Chip Design Challenges with Monozukuri

Anna Fontanelli, Monozukuri’s founder and CEO, is an expert in deep-submicron silicon technology and design tools shares her view on the state of Moore’s Law and challenges surrounding 2.5D integration, 3D chip stacking & advanced packaging, as well as the chip design industry’s startup environment.

Open Source EDA, IP, Cloud-Based Design, Extending Moore’s Law: Pedestal Research’s Laurie Balch Talks Chip Design Trends

As a leading analyst covering the electronic system design segment, Laurie Balch is well steeped in identifying and analyzing technology trends and forecasting new market opportunities. Laurie is now President and Research Director at Pedestal Research.

Pre-Silicon Verification – The Newest Approach to Accelerating Time-to-Market of Advanced Computing Capabilities

“Virtual platform environments that combine the verification capabilities of emulation with the pre-silicon functionality insights available through verification intellectual property (VIP) are an increasingly popular way to get designs verified ahead of the curve of new standards,” Browy says.

Cadence at Forefront in Speeding Chip Design with Machine Learning

Machine learning (ML) and artificial intelligence (AI) have ushered in tremendous opportunities for faster growth, problem-solving and technological development in the electronic system design ecosystem. Cadence Design Systems, Inc., a member of the ESD Alliance, a SEMI Technology Community, is at...

IC Design Crashes Into the 3D Wall: Multiphysics Platforms Ride to the Rescue

Three-dimensional integrated circuits (3D-ICs) are revolutionizing the semiconductor industry. Manufactured by stacking and interconnecting dies so they perform as a single device, 3D-ICs deliver more capabilities by offering higher performance and bandwidth — while also reducing power consumption,...