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March 14, 2024

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Many semiconductor-based systems are moving toward 2.5D and 3D designs consisting of different pre-manufactured chips (chiplets) that perform specific functions. These are often provided by multiple vendors and are typically interconnected using an interposer. However, unlike monolithic multi-function chips, chiplets can be developed anywhere and at any process node. As such, chiplets from untrusted vendors can be unreliable or malicious. Third parties can reverse engineer, overproduce, or steal the IP of chiplets. Consequently, they raise new security challenges for an industry still figuring out ways to effectively mitigate hardware security threats to monolithic chips.

The webinar will focus on the potential threats that occur at the different stages of bringing chiplets to life, including design, assembly, and testing. The panelists will assess current safeguards to mitigate these risks and discuss open challenges for industry and academia.

Time

9:00 am - 10:00 am

Location

Virtual, Online, Pacific Time,
United States

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Agenda

Moderator

9:00 am
Raj Gautam Dutta, CEO, Silicon Assurance
Moderator
Raj Gautam Dutta
CEO
Silicon Assurance

Panelists

Serge Leef
Serge Leef
Head of Secure Microelectronics
Microsoft
Swarup Bhunia, Semmoto Endowed Professor and Director of Warren B. Nelms Institute
Swarup Bhunia
Semmoto Endowed Professor and Director
Warren B. Nelms Institute
Salman Nasir
Salman Nasir
Sr. Technical Program Manager
Battelle
John Hallman
John Hallman
Digital Verification Technology Solutions Manager
Siemens EDA
Steve Carlson
Steve Carlson
Director/Solutions Architect, Aerospace and Defense Solutions
Cadence Design Systems
Ming Zhang
MIng Zhang
VP of R&D Acceleration
PDF Solutions

Registration is free