November 8, 2023
This course will discuss the meaning and the need for advanced packaging such as chiplets, and 3D stacked systems, with a deep dive into hybrid bonding.
Our speaker will be a young, but distinguished engineer from AMD's Advanced packaging Group in Austin, Texas, Dr. Arsalan Alam. Come up to speed quickly and efficiently on the latest thinking on how the semiconductor industry will be delivering more performance and functionality despite the physical limitations of the atom.
Time
10:00 am - 12:00 pm
Location
Virtual,
United States
Abstract:
For many generations of technology nodes, Moore’s Law has reliably delivered the doubling of transistor density every 1.5-2 years while bringing down the cost per transistor. However, in recent advanced nodes, Moore’s Law has slowed down and the cost of advanced node chips has increased.
To keep up with performance demands, manufacturers have continued to increase chip size to have large System on Chip (SoCs), and we have seen chip sizes reach the lithographic reticle limits. Moreover, increasing chip size beyond reticle limits also decreases chip yields and contributes to increasing the cost of manufacturing. Thus, increasing chip sizes beyond reticle limits is not a solution.
The semiconductor industry needs to be on the path of delivering more performance and functionality at reasonable prices despite the slowing of Moore’s Law.
One popular approach the industry is adopting to deliver improved performance is focusing on advanced packaging, including the use of chiplets, hybrid bonding and state of the art 3D stacked systems. This course will discuss the meaning and the need for advanced packaging and dive deeper into each one of these advanced packaging approaches.
Outline
- Need to Advanced Packaging
- Types of Advanced Packaging
- 3D bonding and Intro to Hybrid Bonding for Advanced Packaging
- Types of Hybrid Bonding, Current Status and Challenges
- Future opportunities in Hybrid Bonding
- Summary
Featured Speaker Biography:
Arsalan Alam is a Sr. Packaging Engineer at AMD’s Advanced Packaging Group in Austin, Texas. He completed his PhD in Electrical and Computer Engineering with the Center for Heterogeneous Integration and Performance Scaling (CHIPS) group at the University of California, Los Angeles, in 2021. He received his Master’s degree in Microelectronics and VLSI from IIT Roorkee, India and his Bachelor’s degree in Electronics and Communication Engineering from the Zakir Hussain College of Engineering and Technology, India. His research interest is in advanced packaging, including FOWLP, 2.5D, and 3D. He holds about 20 publications and two patents with multiple patents pending. He was the winner of the IEEE EPS Packaging Vision Award, 2020 and recipient of the Broadcom Foundation Fellowship, 2017-2018.
SEMI Members: $49
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Non-Members: $99
Students: Free
Contact Gity Samadi (gsamadi@semi.org) with a picture of your student ID to receive your discount code.