Axiomise will showcase its portfolio of cutting-edge formal verification solutions that includes training, consulting, services and its custom app formalISA® during RISC-V Summit North America November 7 and 8 in Silicon Valley.
The formalISA® app launched earlier this year is used to formally verify numerous open-source and commercial RISC-V processors, proving the absence of bugs in out-of-order and in-order cores. End users are able to get formal verification results on any RISC-V core by pushing a few buttons and using any formal verification tool.
Axiomise will be in booth #S11 and will feature live demonstrations of the formalISA app and reinforce how it is making formal normal. Axiomise also unveiled earlier this year its RISC-V Studio Portal that displays and explains in detail real-world applications and product demonstrations of how bugs can be caught using formal verification methods.
The RISC-V Summit North America exhibits will be open Tuesday, November 7, from 10:45 am until 7 pm, and Wednesday, November 8, from 10:45am through 4:15 pm at the Santa Clara Convention Center in Santa Clara, Calif. Registration is open.
About formalISA
Axiomise’s formalISA is intelligent debug combined with exhaustive proofs and coverage for end-to-end formal verification. The push-button formal verification solution verifies the architecture and micro-architecture of RISC-V processor cores. It is in use in production environments to formally verify numerous open-source and commercial RISC-V processors by identifying deep corner-case bugs and mathematically proving the absence of bugs on complex out-of-order and in-order cores.
About Axiomise
Axiomise is accelerating formal verification adoption through its unique combination of training, consulting, services and specialized verification solutions for RISC-V. Axiomise was founded by Dr. Ashish Darbari, FBCS, FIETE, DPhil (Oxford), who has been a formal verification practitioner for more than two decades with 60 patents in formal verification and over 70 publications.
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