Many semiconductor-based systems are moving toward 2.5D and 3D designs consisting of different pre-manufactured chips (chiplets) that perform specific functions. These are often provided by multiple vendors and are typically interconnected using an interposer. However, unlike monolithic multi-function chips, chiplets can be developed anywhere and at any process node. As such, chiplets from untrusted vendors can be unreliable or malicious. Third parties can reverse engineer, overproduce, or steal the IP of chiplets. Consequently, they raise new security challenges for an industry still figuring out ways to effectively mitigate hardware security threats to monolithic chips.
The webinar, held on March 14, 2024, focused on the potential threats that occur at the different stages of bringing chiplets to life, including design, assembly, and testing. The panelists assessed current safeguards to mitigate these risks and discussed open challenges for industry and academia.
We encourage registrants to complete the brief chiplet security survey.
Moderator:
- Raj Dutta, CEO, Silicon Assurance
Panelists:
- Swarup Bhunia, Semmoto Endowed Professor and Director, Warren B. Nelms Institute
- Steve Carlson, Director/Solutions Architect, Aerospace and Defense Solutions, Cadence Design Systems
- John Hallman, Digital Verification Technology Solutions Manager, Siemens EDA
- Serge Leef, Head of Secure Microelectronics, Microsoft
- Salman Nasir, Sr. Technical Program Manager, Battelle
- Ming Zhang, VP of R&D, PDF Solutions
Presented by the ESD Alliance, a SEMI Technology Community, in cooperation with Silicon Assurance.
Recorded Webinar
Watch the recording of this informative panel on chiplet security.