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Improving Chip Design and Verification Efficiency with IC Manage

ESD Alliance member company IC Manage enables global teams to efficiently collaborate during design and verification of systems and chips. IC Manage provides design data and IP management, data analytics, hybrid cloud bursting and high-performance computing software to systems and chip companies.

Challenges and Opportunities in Intelligent System Design – Insights from Cadence

SEMI spoke with Rebecca Dobson, Corporate Vice President EMEA at Cadence Design Systems, about semiconductor industry growth drivers and why semiconductor design is crucial to meeting device scaling challenges today and beyond.

Open Source EDA, IP, Cloud-Based Design, Extending Moore’s Law: Pedestal Research’s Laurie Balch Talks Chip Design Trends

As a leading analyst covering the electronic system design segment, Laurie Balch is well steeped in identifying and analyzing technology trends and forecasting new market opportunities. Laurie is now President and Research Director at Pedestal Research.

Chip Design Challenges: Driving the Need for Hardware-Assisted Verification

In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and...