ESD Alliance member company IC Manage is noted for enabling global teams to efficiently collaborate during design and verification of systems and chips. Founded in 2002, IC Manage provides design data and intellectual property (IP) management, data analytics, hybrid cloud bursting and high-performance computing software to systems and semiconductor companies.
Shiv Sikand, a founder of IC Manage, and I recently talked about challenges facing semiconductors design groups managing the flow of data.
Smith: How has managing design and IP data improved large-scale IC designs?
Sikand: Design data management systems have had to continuously keep pace with our industry’s growing design complexity, size and design methodology demands.
Here are three key areas where we’ve seen substantial improvement:
- Git, a distributed version control system that tracks changes in any set of computer files, became a critical element of the data management infrastructure, driven by the need for data management system architectures to support more than binary design data. The architectures must also support text and software data, where Git is in high usage.
- Data analytics can now scale to process and analyze verification data across billions of tests in near real time.
- IP lifecycle management technology has advanced to enable companies to provide IP access to all group members across IP repositories distributed around the world.
Smith: What other insights can you share on the advances in IP Lifecycle Management?
Sikand: IP is the lifeblood of any semiconductor company that wants to leverage it as much as it can to improve design quality, designer efficiency and time to market.
In an independent survey that IC Manage sponsored, we found that two-thirds of design content continues to be from IP reuse, while only 33 percent is new design content. Sixty-one percent of the IP is developed internally with the remainder from third parties. Advanced IP lifecycle management can support both types of IP.
When companies addressed this challenge a decade ago, they worked to bring everything into one centralized database. As these companies grew, including through mergers and acquisitions, fully leveraging IP reuse got harder. Large organizations can now have dozens of different IP repositories in use by diverse design groups across the globe.
Distributed IP repositories have different rules and methodologies. Sometimes the groups even deploy different EDA vendor design tools. A company cannot bring all its IP into one central repository. Design groups don't have the luxury of spending a year configuring and populating it.
For a company to maximize its IP investment today, it must leverage that IP in a distributed way so that each design group can continue its work uninterrupted. This method requires a visualization layer and complex metadata management that will allow design groups to have ready access to all the design IP while aligning with the organization’s security and permission policies.
Enabling company-wide IP reuse necessitates an intricate mix of IP creation best practices, proper IP publishing and cataloging with Google-like IP searchability across all design groups.
Effective lifecycle management requires IP version management, IP usage monitoring and traceability. When an IP creator makes a change, other users need immediate awareness of the change, along with its verification, production and licensing status.
Smith: What design and verification trends are you seeing?
Sikand: We see the industry’s use of the cloud for design and verification continuing to expand globally. The dominant cloud deployment for design and verification continues to be hybrid cloud that combines on-premises compute with cloud compute particularly during periods of peak demand such as regression testing.
In the same survey, we found that 32% of system and semiconductor companies deploy cloud for design or verification to some degree with twice as many companies deploying a hybrid cloud bursting versus an all-cloud design.
Hybrid cloud deployments dynamically allocate resources. The on-premises servers manage the baseline load and when demand spikes, such as during regressions, cloud resources scale to accommodate increased computational needs. The major EDA vendors have been supporting this trend in part by adapting their licensing strategies to be more flexible during these high-demand periods.
The recognition that cloud storage costs can be a significant factor has prompted chip design groups to minimize their reliance on cloud storage. For example, when a full environment is five terabytes, it is expensive to store it for a month or longer. Delete the data, rather than leaving it in the cloud, will slash the storage costs dramatically.
This continuing adoption of hybrid cloud for design and verification design reflects a pragmatic balancing of resource demand variations and cloud costs.
Smith: How has AI, ML and generative AI affected the design flow?
AI is revolutionizing our semiconductor industry, both as AI consumers and as providers of AI technology. We’ve seen Wall Street’s recognition of this in the raised valuation of EDA companies.
From a data management point of view, companies need data to train AI models to maintain their fast pace of innovation. This creates a need to retain and leverage their design data. The thirst for additional compute power for AI is turning companies to the cloud more quickly.
The massive data files pose major hurdles in terms of high cloud storage costs and difficulties achieving a fast enough transfer of large amounts of data, as well as I/O performance for compute jobs.
About Shiv Sikand
As IC Manage founder and EVP, Shiv has been instrumental in achieving its technology leadership in design data management and IP lifecycle management, hybrid cloud technology, and big data analytics for more than 20 years. Sikand collaborates with major systems and semiconductor leaders in deploying IC Manage’s infrastructure and technologies across their enterprises. He received his BSc and MSc degrees in Physics and Electrical Engineering from the University of Manchester, in addition to his postgraduate research in Computer Science.
Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Technology Community.