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Real Intent’s Prakash Narain on Chip Design and Verification’s ‘Shift-Left’ to Reduce Costs and Cycle Times

By Bob Smith
December 5, 2022
Dr. Prakash Narain, president and CEO of Real Intent and a member of the ESD Alliance Governing Council, recently offered insights on the vexing functional verification challenges that consume a significant portion of the chip design cycle.
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Excellicon – Managing Critical Timing Constraints Across Design and Verification to Reduce Timing and Signal Integrity Issues

By Bob Smith
July 5, 2022
Rick Eram, Excellicon’s VP of sales and operations, discusses ways for designers to compare the physical floorplan against the actual register transfer level (RTL) code and constraints, chip design trends and complexity, and a few of his predictions for the design and verification market.
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