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December 5, 2022

Real Intent’s Prakash Narain on Chip Design and Verification’s ‘Shift-Left’ to Reduce Costs and Cycle Times

The Electronic System Design (ESD) ecosystem consists of companies specializing in fields ranging from chip design and verification to software development and includes organizations that provide supporting products and services. Real Intent, a member of the ESD Alliance, a SEMI Technology Community, is a well-known provider of static sign-off tools.

I recently spoke with Prakash Narain, the company’s president and CEO and a member of the ESD Alliance Governing Council, about the vexing functional verification challenges that consume a significant portion of the chip design cycle. What stands out from our discussion are his comments on the move by chip design and verification groups to a shift left methodology where verification and validation testing is done earlier in the design cycle. In the past, engineers performed these functions sequentially, not concurrently. Verifying the design as early as possible can reduce costs and project cycles and the need for respins.

Smith: What trends are you seeing in early functional verification of chip designs? Do any surprise you?

LogoNarain: Early functional verification is finding an increasing role in design methodologies. One way this is happening is that the three traditional workhorses for early functional verification –– simulation, formal verification, and static sign off –– are all extensively deployed.

One trend is that simulation platforms now use machine learning to improve regression efficiency. Additionally, automatically generated assertions are being deployed to improve functional coverage and metastability failure modes in simulation.

New static sign-off trends and advancements include early verification to ensure adherence to specific methodology rules designed to reduce complexity and achieve a left shift. One example is early verification of block abutment for more efficient physical design.

Smith: Do new market segments or applications have different requirements from traditional functional verification needs?

Narain: The more customization a design has, the greater the functional verification effort. For example, standard busses use commercially available standard functional models for simulation, but new models must be developed for custom busses.

Because static verification techniques are focused at the microarchitecture level, they can be applied across various design types without requiring customization. Thus, special customization is not required, regardless of whether it’s an artificial intelligence (AI) chip, a CPU, or a GPU. This commonality allows static sign-off tools to be highly automated and more efficient out-of-the-box than dynamic verification.

Smith: Has Real Intent identified new market domains or applications in need of a static sign-off methodology? If so, what are they?

HSNarain: New failure modes continue to emerge, primarily driven by design complexity. This has created an immense opportunity to enable an even greater shift left for static sign-off.

With regards to failure modes, static sign-off initially started with clock domain crossing sign-off. Reset domain crossing is the newest static sign-off application. Additionally, design initialization and low-power sign-off are commonly used.

In terms of shifting left in functional verification, static sign-off technologies such as register transfer level (RTL) linting and early design for test (DFT) are already available, with new opportunities in areas such as connectivity and glitch sign-off just introduced.

Smith: What’s new with the static sign-off domain?

Narain: First, each static sign-off application must manage higher design complexity and capacity requirements by supporting divide and conquer in the form of hierarchical analysis. Additionally, each application must support multiple modes of operation. These are both occurring while we also continuously push for greater capacity, performance, accuracy, quality of results, and efficient debug to reduce turnaround time.

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Hierarchical analysis requires accurate abstraction, with custom hierarchical analysis needed for each application. For example, different cross-domain clock (CDC) abstraction models can have different ranges of accuracy, while reset domain crossing (RDC) abstraction models require a more complex, database-driven approach.

Multimode analysis means different things for different domains. CDC analysis must support multiple clock modes, along with exclusive relationships between asynchronous clocks. RDC analysis must support multiple scenarios, RTL linting will support multiple policies, and DFT analysis will have multiple test modes. All multimode analysis must produce consolidated reports.

The biggest innovations for static sign off are hierarchy, multi-mode analysis, and efficient debug for faster turnaround time.

Smith: Verification represents a significant portion of the chip design cycle. What do you attribute that to? Is the percentage getting larger or shrinking?

Narain: Verification is an open-ended problem growing non-linearly with increasing complexity. As a result, the verification effort has been increasing as a percentage of the overall chip development effort.

ImageAs an industry, we’ve been successful in containing that growth by creating more powerful simulators and emulators and using massively parallel deployment.

Additionally, shift left enabled by new methodologies and tools such as static sign-off is playing a critical role in containing this verification complexity.

Smith: Do you see open-source tools gaining traction in early functional verification?

Narain: I don’t see this happening anytime soon. Functional verification applications are highly complex; achieving continuous advancement requires ongoing partnerships with customers and an extremely high level of expert support.

About Dr. Prakash Narain

Dr. Prakash Narain is president and CEO of Real Intent. He has hands-on experience in all aspects of IC design and CAD tool design and methodology from his work at AMD, IBM and Sun. He was the project leader for test and verification for UltraSPARC III at Sun Microsystems. He was an architect of the Mercury Design System at AMD and architected and developed CAD tools for test and verification for IBM EDA. Dr. Narain has a Ph.D. from the University of Illinois at Champaign-Urbana, where his thesis focus was on algorithms for high-level testing and verification.

Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.