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Speeding the Path to Industry Standardization with Accellera

Accellera Systems Initiative is a standards organization well-regarded by the EDA ecosystem that’s also served by the ESD Alliance, a SEMI Technology Community. Lu Dai, Senior Director of Technical Standards at Qualcomm, has chaired the Accellera Board of Directors since 2017.

Real Intent’s Prakash Narain on Chip Design and Verification’s ‘Shift-Left’ to Reduce Costs and Cycle Times

Dr. Prakash Narain, president and CEO of Real Intent and a member of the ESD Alliance Governing Council, recently offered insights on the vexing functional verification challenges that consume a significant portion of the chip design cycle.

ESD Alliance Combats Piracy

ESD Alliance’s License Management and Anti-Piracy (LMA) Committee has worked with member companies Cadence, Siemens EDA and Synopsys to develop a protocol for use with software license management systems to provide strong protection against piracy by defining how servers can be uniquely identified.

Excellicon – Managing Critical Timing Constraints Across Design and Verification to Reduce Timing and Signal Integrity Issues

Rick Eram, Excellicon’s VP of sales and operations, discusses ways for designers to compare the physical floorplan against the actual register transfer level (RTL) code and constraints, chip design trends and complexity, and a few of his predictions for the design and verification market.

Methodics by Perforce Surveys Semiconductor Design Professionals on Product Lifecycle Management

Product lifecycle management is a well-adopted methodology used in mechanical design. Until recently, it was not widely used in the semiconductor industry. That all changed when Methodics created intellectual property lifecycle management for tracking and analysis of semiconductor IP and design.

Semiconductor Manufacturing, Supply Chain Challenges and Startups in France: Aselta Weighs in

The increasing complexity of IC manufacturing poses a number of challenges including the mask data preparation required to enable technology improvements such as multi-beam (MB) mask writers and extreme ultraviolet (EUV) lithography. Thiago Figueiro, VP of Sales & Marketing of Aselta weighs in.

Electrostatic Energy Drives Higher Power-Efficiency and Performance in Chip Design

Azeez Bhavnagarwala, Metis’ founder and CEO, speaks about advanced CMOS Memory and Arithmetic component intellectual property (IP) to improve energy efficiency and performance of processors.

Conquering 2.5D and 3D Chip Design Challenges with Monozukuri

Anna Fontanelli, Monozukuri’s founder and CEO, is an expert in deep-submicron silicon technology and design tools shares her view on the state of Moore’s Law and challenges surrounding 2.5D integration, 3D chip stacking & advanced packaging, as well as the chip design industry’s startup environment.

Open Source EDA, IP, Cloud-Based Design, Extending Moore’s Law: Pedestal Research’s Laurie Balch Talks Chip Design Trends

As a leading analyst covering the electronic system design segment, Laurie Balch is well steeped in identifying and analyzing technology trends and forecasting new market opportunities. Laurie is now President and Research Director at Pedestal Research.

Pre-Silicon Verification – The Newest Approach to Accelerating Time-to-Market of Advanced Computing Capabilities

“Virtual platform environments that combine the verification capabilities of emulation with the pre-silicon functionality insights available through verification intellectual property (VIP) are an increasingly popular way to get designs verified ahead of the curve of new standards,” Browy says.