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Real Intent’s Prakash Narain on Chip Design and Verification’s ‘Shift-Left’ to Reduce Costs and Cycle Times

Dr. Prakash Narain, president and CEO of Real Intent and a member of the ESD Alliance Governing Council, recently offered insights on the vexing functional verification challenges that consume a significant portion of the chip design cycle.

S2C Paves Way to Digital Innovation with Cutting-Edge Chip Design Verification Solutions

Founded in 2004, S2C’s worldwide customer base uses its desktop and enterprise field programmable gate array (FPGA) prototyping tools to verify system on chip (SoC) and application-specific integrated circuit (ASIC) designs will work as intended.

Excellicon – Managing Critical Timing Constraints Across Design and Verification to Reduce Timing and Signal Integrity Issues

Rick Eram, Excellicon’s VP of sales and operations, discusses ways for designers to compare the physical floorplan against the actual register transfer level (RTL) code and constraints, chip design trends and complexity, and a few of his predictions for the design and verification market.

How Synopsys is Transforming the Chip Development Landscape Via the Cloud

Vikram Bhatia, Director of the Synopsys Cloud Go-to-Market and Product Strategy, discusses leveraging a flexible, pay-per-use approach to fuel the next phase of semiconductor innovation - bring your own cloud (BYOC) and software as a service (SaaS) deployment model.

Open Platforms are the Foundation for Advanced System Design

A critical foundation for success in this new multiphysics reality is the development of open, extensible and cloud-optimized platforms that enable many different tools and data sets to work together and build towards a realistic and accurate simulation of physical reality.

From Fledgling Business to the Core of Chips: CAST Bears Witness to Silicon IP Market Maturation

In the early 1990s, engineers of varying degrees of skill with a powerful PC set up shop designing and selling blocks or libraries of reusable components with a defined interface and behavior. These blocks, known as intellectual property, or IP, were then (and still are) integrated into a larger...

Homegrown EDA Tools, Open Source, Starting an EDA Company: Verific on Chip Design Trends

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia,...

Chip Design Challenges: Driving the Need for Hardware-Assisted Verification

In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and...